Static random access memories (SRAMs), when used in certain applications such as satellite communications and tactical weapons, require a high degree of immunity from single event upsets (SEUs). An SEU results in the corruption of data known as a "soft error", and is the result of a charged particle radiation hit on a charged node within the cell. Although both static and dynamic random access memories are vulnerable to SEUs, this discussion will be limited to SRAMs.
FIG. 1 is a schematic representation of a typical cross-coupled six-transistor SRAM cell. Let us assume that, with transistors Q1 and Q4 turned on, transistors Q2 and Q3 turned off, both NODE A and NODE D at a Vcc voltage of +5 volts, and both NODE B and NODE C grounded to 0 volts, an information bit value of "1" is stored within the cell. If a charged particle of radiation (such as an alpha particle) were to impact NODE A, hole-electron pairs would be generated in the cell substrate, which would allow the charge on NODE A to partially or completely dissipate. This reduction in charge on NODE A will propagate to NODE D at a rate faster than transistor Q1 can recharge NODE A. If the charge on NODE A has dropped to near 0 volts, the charge on NODE D will be pulled rapidly to near 0 volts, causing transistor Q3 to turn on and transistor Q4 to turn off. NODE B and NODE C will then be charged to Vcc, thus turning transistor Q1 off and transistor Q2 on. This new latched state of the cell will no longer represent a bit value of "1", but rather a bit value of "0". By definition, an SEU has occurred.
A cross-coupled resistor design has been used extensively for the past several years to dramatically reduce the soft error rate of SRAM cells. By connecting resistors having a resistance on the order of 100K ohms between opposite nodes of the four-transistor storage latch, the cross-coupling RC time constant is increased. In the circuit of FIG. 1, one resistor would be placed between NODE A and NODE D, while another would be placed between NODE B and NODE C. Such a design modification will delay the propagation of a rapid change in voltage on one side of two interconnected nodes by several nanoseconds. Thus, in our example of a hit on NODE A, transistor Q1 will restore the +5 volt charge to NODE A before its SEU-induced low-voltage charge can create a latch-reversing voltage change at NODE D.
In the past, various processes have been used to create these high-value inter-nodal coupling resistors from the same layer of polycrystalline silicon (poly) that is used to form the gates of the cell's transistors. While such processes are generally successful for lower integration levels, they are beset by a number of drawbacks as device dimensions shrink at higher integration levels. One of the drawbacks is the inability to accurately control grain-boundary-assisted diffusion between the heavily-doped regions destined to be transistor gates and the lightly-doped regions destined to be inter-nodal coupling resistors within the single poly layer. Such diffusion can dramatically change the sheet resistance value of the resistor poly regions, and in extreme cases may even alter the work function of the gate poly regions, which affects threshold voltage. Another drawback is the inability to vary the thickness of the resistive layer independently of the gate layer, since they are one and the same. Hence, thickness is not available as a degree of freedom for controlling the final sheet resistance. An additional drawback is the necessity of using a masked implant to obtain two regions of different dopant concentration in the poly-1 layer before it is patterned.
In order to increase the operating speed of SRAMs, the diffusion and polysilicon interconnect regions are silicided with titanium in a self-aligned process, commonly referred to as a salicide process.
The processing of low sheet resistance salicided poly for speed and high sheet resistance unsalicided poly for radiation tolerance are inconsistent with one another unless a unique process flow is created which can simultaneously accommodate these disparate elements.
It would be highly desirable to develop a process for creating inter-nodal coupling resistors which is more compatible with high-speed/high-density circuit design, and which eliminates the problems discussed above.